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==Core Memory== | ==Core Memory== | ||
Memory storage for main core usage is provided by 2,048 dedicated modules of 144 isolinear optical storage chips. Under [[LCARS]] software control, these modules provide average dynamic access to memory at 4,600 kiloquads/sec. Total storage capacity of each module is about 630,000 kiloquads, depending on software configuration. The main cores are tied into the ship's [[Optical Data Network]] by means of a series of MJL junctions links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary but the resulting increase in processing speed from the faster-than-light elements more than compensates. | Memory storage for main core usage is provided by 2,048 dedicated modules of 144 isolinear optical storage chips. Under [[LCARS]] software control, these modules provide average dynamic access to memory at 4,600 kiloquads/sec. Total storage capacity of each module is about 630,000 kiloquads, depending on software configuration. The main cores are tied into the ship's [[Engineering_Utilities#Optical_Data_Network|Optical Data Network]] by means of a series of MJL junctions links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary but the resulting increase in processing speed from the faster-than-light elements more than compensates. | ||
==Sub Processors== | ==Sub Processors== | ||