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[[Image:Computerc.jpg| | {{academy}}[[Image:Computerc.jpg|left]]The main computer is probably the most important operational element of a starship next to the crew. The computer is directly analogous to the autonomic nervous system of a living being, and is responsible in some way for the operation of every other system of the ship. | ||
The main computer is probably the most important operational element of a starship next to the crew. The computer is directly analogous to the autonomic nervous system of a living being, and is responsible in some way for the operation of every other system of the ship. | |||
Crew interface for the main computer is provided by the Library Computer Access and Retrieval System software(LCARS). It provides both keyboard and verbal interface ability, incorporating highly sophisticated artificial intelligence routines and graphic display organization for maximum crew ease-of-use. | Crew interface for the main computer is provided by the Library Computer Access and Retrieval System software(LCARS). It provides both keyboard and verbal interface ability, incorporating highly sophisticated artificial intelligence routines and graphic display organization for maximum crew ease-of-use. | ||
==Computer Cores== | ==Computer Cores== | ||
The heart of the main system is a set of three main processing cores. Any of these cores is able to handle the primary operational computing load of the entire vessel. Two of these cores are located near the center of the Primary Hull under the Engineering Hull.Each main core incorporates a series of miniature subspace field generators, which creates a symmetrical field distortion of 3350 millicochranes within the faster-than-light core elements.This permits the transmission and processing of optical data within the core at rates significantly exceeding lightspeed.The two main cores in the Primary Hull run in parallel clock-sync with each other, proceeding 100% redundancy. In the event of any failure in either core, the other core is able to instantly assume the total computing load for the ship with no interruption, although some secondary and recreational functions may be suspended. The third core, located in the engineering hull, serves as a backup to the first two. Core elements are based on faster -than -light nanaprocessor units arranged into optical translator clusters of 1,025 segments. In turn, clusters are grouped into processing modules composed of 256 clusters controlled by a bank of sixteen isolinear chips. Each core comprises seven primary and three upper levels, each level containing an average of four modules. | The heart of the main system is a set of three main processing cores. Any of these cores is able to handle the primary operational computing load of the entire vessel. Two of these cores are located near the center of the Primary Hull under the Engineering Hull.Each main core incorporates a series of miniature subspace field generators, which creates a symmetrical field distortion of 3350 millicochranes within the faster-than-light core elements.This permits the transmission and processing of optical data within the core at rates significantly exceeding lightspeed.The two main cores in the Primary Hull run in parallel clock-sync with each other, proceeding 100% redundancy. In the event of any failure in either core, the other core is able to instantly assume the total computing load for the ship with no interruption, although some secondary and recreational functions may be suspended. The third core, located in the engineering hull, serves as a backup to the first two. Core elements are based on faster -than -light nanaprocessor units arranged into optical translator clusters of 1,025 segments. In turn, clusters are grouped into processing modules composed of 256 clusters controlled by a bank of sixteen isolinear chips. Each core comprises seven primary and three upper levels, each level containing an average of four modules. | ||
==Core Memory== | ==Core Memory== | ||
Memory storage for main core usage is provided by 2,048 dedicated modules of 144 isolinear optical storage chips. Under LCARS software control, these modules provide average dynamic access to memory at 4,600 kiloquads/sec. Total storage capacity of each module is about 630,000 kiloquads, depending on software configuration. The main cores are tied into the ship's optical data network by means of a series of MJL junctions links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary but the resulting increase in processing speed from the faster-than-light elements more than compensates. | Memory storage for main core usage is provided by 2,048 dedicated modules of 144 isolinear optical storage chips. Under LCARS software control, these modules provide average dynamic access to memory at 4,600 kiloquads/sec. Total storage capacity of each module is about 630,000 kiloquads, depending on software configuration. The main cores are tied into the ship's optical data network by means of a series of MJL junctions links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary but the resulting increase in processing speed from the faster-than-light elements more than compensates. | ||
==Sub Processors== | ==Sub Processors== | ||
A network of many quadritonic optical subprocessors is distributed throughout the ship sections, augmenting the main cores. Within the habitable volume of the ship, most of these sub processors are located near main corridor junctions. While these subprocessors do not employ faster-than-light elements, the distributed processing network improves overall system response and provides redundancy in emergency situations. Each subprocessor is linked into the optical data network, and most also have a dedicated optical link to one or more of the main cores. The main Bridge and the Battle Bridge have seven dedicated and twelve shared subprocessors, which permit operations even in the event of main core failure. The subprocessors are linked to the main cores by means of protected optical conduits, which provide alternate control linkages in the event of primary optical data network failure. Further redundancy is provided by dedicated short-range radio frequency links, providing emergency data communications with the bridge. Additional dedicated subprocessors can be installed as needed to support mission-specific operations. Virtually every control panel and terminal within the ship is linked to a subprocessor or directly into the optical data network. Each active panel is continually polled by LCARS at 30 millisecond intervals so that the local subprocessor or the main core is informed of all verbal and keyboard inputs. Short-range RF data links are available throughout the ship to provide information transmission to portable and handheld devices such as tricorders and personal access display devices (PADD). | A network of many quadritonic optical subprocessors is distributed throughout the ship sections, augmenting the main cores. Within the habitable volume of the ship, most of these sub processors are located near main corridor junctions. While these subprocessors do not employ faster-than-light elements, the distributed processing network improves overall system response and provides redundancy in emergency situations. Each subprocessor is linked into the optical data network, and most also have a dedicated optical link to one or more of the main cores. The main Bridge and the Battle Bridge have seven dedicated and twelve shared subprocessors, which permit operations even in the event of main core failure. The subprocessors are linked to the main cores by means of protected optical conduits, which provide alternate control linkages in the event of primary optical data network failure. Further redundancy is provided by dedicated short-range radio frequency links, providing emergency data communications with the bridge. Additional dedicated subprocessors can be installed as needed to support mission-specific operations. Virtually every control panel and terminal within the ship is linked to a subprocessor or directly into the optical data network. Each active panel is continually polled by LCARS at 30 millisecond intervals so that the local subprocessor or the main core is informed of all verbal and keyboard inputs. Short-range RF data links are available throughout the ship to provide information transmission to portable and handheld devices such as tricorders and personal access display devices (PADD). | ||
Revision as of 04:07, 19 August 2004
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The main computer is probably the most important operational element of a starship next to the crew. The computer is directly analogous to the autonomic nervous system of a living being, and is responsible in some way for the operation of every other system of the ship.
Crew interface for the main computer is provided by the Library Computer Access and Retrieval System software(LCARS). It provides both keyboard and verbal interface ability, incorporating highly sophisticated artificial intelligence routines and graphic display organization for maximum crew ease-of-use.
Computer Cores
The heart of the main system is a set of three main processing cores. Any of these cores is able to handle the primary operational computing load of the entire vessel. Two of these cores are located near the center of the Primary Hull under the Engineering Hull.Each main core incorporates a series of miniature subspace field generators, which creates a symmetrical field distortion of 3350 millicochranes within the faster-than-light core elements.This permits the transmission and processing of optical data within the core at rates significantly exceeding lightspeed.The two main cores in the Primary Hull run in parallel clock-sync with each other, proceeding 100% redundancy. In the event of any failure in either core, the other core is able to instantly assume the total computing load for the ship with no interruption, although some secondary and recreational functions may be suspended. The third core, located in the engineering hull, serves as a backup to the first two. Core elements are based on faster -than -light nanaprocessor units arranged into optical translator clusters of 1,025 segments. In turn, clusters are grouped into processing modules composed of 256 clusters controlled by a bank of sixteen isolinear chips. Each core comprises seven primary and three upper levels, each level containing an average of four modules.
Core Memory
Memory storage for main core usage is provided by 2,048 dedicated modules of 144 isolinear optical storage chips. Under LCARS software control, these modules provide average dynamic access to memory at 4,600 kiloquads/sec. Total storage capacity of each module is about 630,000 kiloquads, depending on software configuration. The main cores are tied into the ship's optical data network by means of a series of MJL junctions links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary but the resulting increase in processing speed from the faster-than-light elements more than compensates.
Sub Processors
A network of many quadritonic optical subprocessors is distributed throughout the ship sections, augmenting the main cores. Within the habitable volume of the ship, most of these sub processors are located near main corridor junctions. While these subprocessors do not employ faster-than-light elements, the distributed processing network improves overall system response and provides redundancy in emergency situations. Each subprocessor is linked into the optical data network, and most also have a dedicated optical link to one or more of the main cores. The main Bridge and the Battle Bridge have seven dedicated and twelve shared subprocessors, which permit operations even in the event of main core failure. The subprocessors are linked to the main cores by means of protected optical conduits, which provide alternate control linkages in the event of primary optical data network failure. Further redundancy is provided by dedicated short-range radio frequency links, providing emergency data communications with the bridge. Additional dedicated subprocessors can be installed as needed to support mission-specific operations. Virtually every control panel and terminal within the ship is linked to a subprocessor or directly into the optical data network. Each active panel is continually polled by LCARS at 30 millisecond intervals so that the local subprocessor or the main core is informed of all verbal and keyboard inputs. Short-range RF data links are available throughout the ship to provide information transmission to portable and handheld devices such as tricorders and personal access display devices (PADD).